Silicon-based integrated circuit (IC) devices, in particular, a metal-oxide semiconductor (MOS) device, e.g., a field effect transistor (FET) or a metal-oxide semiconductor field effect transistor (MOSFET) are widely used in many consumer and commercial applications. These devices have been fabricated such that the throughput can decrease and a high speed, a high integrity and an enhanced performance can be obtained.
FIG. 1A shows a conventional planar type FET. Referring to FIG. 1A, the planar type FET is formed on a substrate 10 having heavily doped source (S) and drain (D) regions 12 separated by a lightly doped channel region 18. Halo regions 20 also may be provided. The channel region 18 is controlled by a gate electrode 14 electrically isolated from the channel region 18 by a gate insulating layer 16.
As the integration density continues to increase, a variety of problems deteriorating the transistor characteristics may occur. For instance, as the channel length of the FET is gradually decreased, problems including short channel effects, such as punch-through, drain induced barrier lowering (DIBL), subthreshold swing and the like, an increase in parasitic capacitance (junction capacitance) between the junction region and a substrate, a leakage current increase, etc., may occur.
Accordingly, a variety of structures, processes and equipment to replace the conventional planar type FET have been developed. For example, a variety of transistors including an ultra-thin body transistor in which a channel region 18 is disposed in an ultra thin layer 12 as shown in FIG. 1B, and a double-gate transistor having one channel region 18 controlled by two gates 14a and 14b separated from the channel region 18 by gate insulating layers 16a and 16b as shown in FIG. 1C, have been designed and proposed to overcome the potential problems of the conventional planar type bulk-FET.
A FinFET process, in which a channel is formed in a semiconductor “Fin”, a gate insulating layer is formed on the semiconductor Fin, and a gate electrode is formed around the semiconductor Fin has also been proposed. FIGS. 2A and 2D show sectional views of semiconductor substrates used in main steps of a conventional method of forming a conventional Fin transistor using a bulk silicon substrate.
First, referring to FIG. 2A, a silicon substrate exposed by an etch mask 13 formed thereon is anisotropically etched to form a silicon fin 15. The etch mask is generally formed of silicon nitride. At this time, a thermal oxide may be formed between the silicon nitride and the silicon substrate. Thereafter, a device isolation layer 17 is formed for an electrical insulation between adjacent silicon fins, as shown in FIG. 2B.
Referring to FIG. 2C, the device isolation layer 17 is partially removed such that sidewalls of the silicon fin 15, which are being used as an active region, are exposed. The exposed sidewalls of the silicon fin 15 serve as a channel region.
Referring to FIG. 2D, a gate insulating layer 19 is formed on the exposed sidewalls of the fin 15, and then a gate electrode 21 is also formed. As a result, a double-gate FinFET in which both sidewalls of the silicon fin 15 are controlled by the gate electrode 21 is formed.
According to the conventional method of forming the double-gate FinFET, while the step of partially removing the device isolation layer 17 is performed, a junction between the etch mask 13 and the substrate 10 may be weakened. Since the device isolation layer 17 may be an oxide-based insulator, the thermal oxide of the etch mask 13 on some of the semiconductor fins may be removed together with the device isolation layer. Especially, as the device is highly integrated and the width of the semiconductor fin decreases, the possibility that the etch mask 13 is detached from surfaces of some of the semiconductor fins may further increase. Also, while the step of partially removing the device isolation layer 17 is performed, the semiconductor fin 15 may be etch-damaged, so that the device reliability may be impacted.
Attempts have been made to apply a CMOS technique using the semiconductor fin to non-volatile memory devices. For example, in U.S. Pat. Nos. 6,768,158 and 6,657,252, non-volatile devices using a semiconductor fin are disclosed. However, in the above references, a silicon-on-insulator (SOI) substrate may be used to form such a semiconductor fin. The SOI substrate may be expensive and may show a floating effect, compared with bulk silicon substrates. Other techniques for manufacturing non-volatile memory devices are described in Korean Publication Number 1999-0075210, published Oct. 15, 1999 to Yoon, entitled Non-Volatile Memory Cell and Manufacturing Method Thereof. 